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d a t a sh eet preliminary speci?cation file under integrated circuits, ic01 1998 aug 28 integrated circuits UDA1335H universal serial bus (usb) audio playback recording peripheral (aprp)
1998 aug 28 2 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H features general usb stereo audio record and playback system with 20 bits analog-to-digital conversion (with 5 to 55 khz sample frequency range) and adaptive 20 bits digital-to-analog conversion (with 5 to 55 khz sample frequency range) with integrated filtering usb-compliant audio/hid device supports 12 mbits/s full speed serial data transmission fully automatic plug-and-play operation supports multiple audio data formats (8, 16 and 24 bits) 5.0 and 3.3 v power supply low power consumption efficient power management on-chip master clock oscillators, only an external crystal is required high linearity wide dynamic range superior signal-to-noise ratio low total harmonic distortion supports headphone and line output partly programmable usb descriptors and configuration via the i 2 c-bus. sound processing (for digital-to analog conversion) separate digital volume control for left and right channel soft mute digital bass and treble tone control external digital sound processor (dsp) option possible via standard i 2 s-bus or japanese digital i/o format selectable clipping prevention selectable dynamic bass boost (dbb) on-chip digital de-emphasis. document references usb specification usb device class definition for audio devices device class definition for human interface devices (hid) usb hid usage table usb common class specification . general description the UDA1335H is a stereo cmos codec incorporating bitstream converters designed for implementation in usb-compliant audio peripherals and multimedia audio applications. the UDA1335H is an adaptive asynchronous sink usb audio device with a continuous sampling frequency range from 5 to 55 khz. it contains a usb interface, an embedded microcontroller, an analog-to-digital interface (adif) and an asynchronous digital-to-analog converter (adac). the usb interface is the interface between the usb, the adif, the adac and the microcontroller. the usb interface consists of an analog front-end and a usb processor. the analog front-end transforms the differential usb data into a digital data stream. the usb processor buffers the incoming and outgoing data from the analog front-end and handles all low-level usb protocols. the usb processor selects the relevant data from the universal serial bus, performs an extensive error detection and separates control information (input and output) and audio information (input and output). the control information is made accessible to the microcontroller. the audio information received from the pc becomes available at the digital i/o output or is fed directly to the adac. the audio information to be transmitted to the pc is delivered by the adif or by the digital i 2 s-bus interface. the microcontroller handles the high-level usb protocols, translates the incoming control requests and manages the user interface via general purpose pins and an i 2 c-bus.
1998 aug 28 3 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H the firmware for the microcontroller must be located in an external (e)prom. the adac enables the wide and continuous range of input sampling frequencies. by means of a sample frequency generator (sfg), the adac is able to reconstruct the average sample frequency from the incoming audio samples. the adac also performs the sound processing. the adac consists of a fifo, a unique audio feature processing dsp, the sfg, digital upsampling filters, a variable hold register, a noise shaper (ns) and a filter stream dac (fsdac) with integrated filter and line output drivers. the audio information is applied to the adac via the usb processor or via the digital i/o input. the adif consists of an programmable gain amplifier (pga), an analog-to-digital converter (adc) and a decimator filter (df). an analog phase lock loop (apll) or oscillator is used for clocking the adif. the clock frequency for the adif can be controlled via the microcontroller. several clock frequencies are possible for sampling the analog input signal at different sampling rates. via the digital i/o-bus, an external dsp can be used for adding extra sound processing features for the audio received from the pc. the UDA1335H supports the digital i/o and the i 2 s-bus interface, with standard i 2 s-bus data input format and the lsb justified serial data input format with word lengths of 16, 18 and 20 bits. the wide dynamic range of the bitstream conversion technique used in the UDA1335H guarantees a high audio sound quality. applications usb monitors usb speakers usb headsets usb telephone/answering machines usb links in consumer audio devices. ordering information type number package name description version UDA1335H qfp64 plastic quad ?at package; 64 leads (lead length 1.95 mm); body 14 20 2.8 mm sot319-2
1998 aug 28 4 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H quick reference data note 1. exclusive the i dde current which depends on the components connected to the i/o pins. symbol parameter conditions min. typ. max. unit supplies v dde supply voltage periphery 4.75 5.0 5.25 v v ddi supply voltage core 3.0 3.3 3.6 v i dd(tot) total supply current - 60 tbf ma i dd(tot)(ps) total supply current in power-saving mode note 1 - 360 -m a dynamic performance dac (thd + n)/s total harmonic distortion plus noise-to-signal ratio f s = 44.1 khz; r l =5k w f i = 1 khz (0 db) -- 90 - 80 db - 0.0032 0.01 % f i = 1 khz ( - 60 db) -- 30 - 20 db - 3.2 10 % s/n signal-to-noise ratio at bipolar zero a-weighted at code 0000h 90 95 - dba v o(fs)(rms) full-scale output voltage (rms value) v dd = 3.3 v - 0.66 - v dynamic performance pga and adc (thd + n)/s total harmonic distortion plus noise-to-signal ratio f s = 44.1 khz; pga gain = 0 db f i = 1 khz; (0 db); v i = 1.0 v (rms) -- 85 - 80 db - 0.0056 0.01 % f i = 1 khz ( - 60 db) -- 30 - 20 db - 3.2 10.0 % s/n signal-to-noise ratio v i = 0.0 v 90 95 - dba general characteristics f i(s) audio input sample frequency 5 - 55 khz t amb operating ambient temperature 0 25 70 c
1998 aug 28 5 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H block diagram fig.1 block diagram. handbook, full pagewidth mbk838 timing analog pll osc 48 mhz osc adc 24 27 25 26 28 52 53 54 55 63 1 2 13 17 15 11 12 9 10 32 33 38 39 42 44 analog front-end usb-processor digital i/o fifo audio feature processing dsp upsample filters variable hold register 3rd-order noise shaper reference voltage 57 59 61 43 47 8 6 micro- controller test control block sample frequency generator mux i 2 s-bus interface decimator filter pga left sd adc pga right sd adc left dac right dac 49 51 45, 46 41 40 v ref(ad) v ref(da) 37 34 36 35 4 21 19 n.c. UDA1335H + - - + vrn vinr v ssa2 vinl v ssa1 v dda1 voutr rtcb gp4/bcko shtcb d - 7, 5, 3, 64, 62, 60, 58, 56 p0.7 to p0.0 14, 16, 18, 20, 22, 23, 29, 30 p2.0 to p2.7 d + v ddi v ssi v dde gp1/di gp0/bcki v dda2 bck 48 ea 50 ale ws da 31 psen v ssa3 xtal2a v dda3 vrp gp2/do gp3/wso xtal1a sda v ssx xtal1b xtal2b clk v ddx v sso voutl tc scl v ddo v sse gp5/wsi
1998 aug 28 6 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H pinning symbol pin qfp64 i/o description gp3/wso 1 i/o general purpose pin 3 or word select output gp4/bcko 2 i/o general purpose pin 4 or bit clock output p0.5 3 i/o port 0.5 of the microcontroller shtcb 4 i shift clock of the test control block (active high) p0.6 5 i/o port 0.6 of the microcontroller d - 6 i/o negative data line of the differential data bus, conforms to the usb standard p0.7 7 i/o port 0.7 of the microcontroller d+ 8 i/o positive data line of the differential data bus, conforms to the usb standard v ddi 9 - digital supply voltage for core v ssi 10 - digital ground for core v sse 11 - digital ground for i/o pads v dde 12 - digital supply voltage for i/o pads gp1/di 13 i/o general purpose pin 1 or data input p2.0 14 i/o port 2.0 of the microcontroller gp5/wsi 15 i/o general purpose pin 5 or word select input p2.1 16 i/o port 2.1 of the microcontroller gp0/bcki 17 i/o general purpose pin 0 or bit clock input p2.2 18 i/o port 2.2 of the microcontroller scl 19 i/o serial clock line i 2 c-bus p2.3 20 i/o port 2.3 of the microcontroller sda 21 i/o serial data line i 2 c-bus p2.4 22 i/o port 2.4 of the microcontroller p2.5 23 i/o port 2.5 of the microcontroller v ssx 24 - crystal oscillator ground (48 mhz) xtal1b 25 i crystal input (analog; 48 mhz) xtal2b 26 o crystal output (analog; 48 mhz) clk 27 o 48 mhz clock output signal v ddx 28 - supply crystal oscillator (48 mhz) p2.6 29 i/o port 2.6 of the microcontroller p2.7 30 i/o port 2.7 of the microcontroller psen 31 i/o program store enable (active low) v ddo 32 - supply voltage for operational ampli?er v sso 33 - operational ampli?er ground voutl 34 o voltage output left channel tc 35 i test control input (active high) rtcb 36 i asynchronous reset input of the test control block (active high) voutr 37 o voltage output right channel v dda1 38 - analog supply voltage 1 v ssa1 39 - analog ground 1
1998 aug 28 7 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H v ref(da) 40 o reference voltage output dac v ref(ad) 41 o reference voltage output adc v dda2 42 - analog supply voltage 2 vinl 43 i input signal left channel pga v ssa2 44 - analog ground 2 n.c. 45 - not connected n.c. 46 - not connected vinr 47 i input signal right channel pga ea 48 - external access (active low) vrn 49 i negative reference input voltage adc ale 50 - address latch enable (active high) vrp 51 i positive reference input voltage adc v dda3 52 - supply voltage for crystal oscillator and analog pll xtal2a 53 o crystal output (analog; adc) xtal1a 54 i crystal input (analog; adc) v ssa3 55 - crystal oscillator and analog pll ground p0.0 56 i/o port 0.0 of the microcontroller da 57 i data input (digital) p0.1 58 i/o port 0.1 of the microcontroller ws 59 i word select input (digital) p0.2 60 i/o port 0.2 of the microcontroller bck 61 i bit clock input (digital) p0.3 62 i/o port 0.3 of the microcontroller gp2/do 63 i/o general purpose pin 2 or data output p0.4 64 i/o port 0.4 of the microcontroller symbol pin qfp64 i/o description
1998 aug 28 8 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H fig.2 pin configuration. handbook, full pagewidth UDA1335H mbk841 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 gp3/wso gp4/bcko p0.5 shtcb p0.6 d - p0.7 d + v ddi v ssi v sse v dde gp1/di p2.0 gp5/wsi p2.1 gp0/bcki p2.2 scl vrp ale vrn ea vinr n.c. n.c. v ssa2 vinl v dda2 v ref(ad) v ref(da) v ssa1 v dda1 voutr rtcb tc voutl v sso 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 p0.4 gp2/do p0.3 bck p0.2 ws p0.1 da p0.0 v ssa3 xtal1a xtal2a v dda3 p2.3 sda p2.4 p2.5 v ssx xtal1b xtal2b clk v ddx p2.6 p2.7 psen v ddo
1998 aug 28 9 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H functional description the universal serial bus (usb) data and power is transferred via the usb over a 4-wire cable. the signalling occurs over two wires and point-to-point segments. the signals on each segment are differentially driven into a cable of 90 w intrinsic impedance. the differential receiver features input sensitivity of at least 200 mv and sufficient common mode rejection. the analog front-end the analog front-end is an on-chip generic usb transceiver. it is designed to allow voltage levels up to v dd from standard or programmable logic to interface with the physical layer of the usb. it is capable of receiving and transmitting serial data at full speed (12 mbits/s). the usb processor the usb processor forms the interface between the analog front-end, the adif, the adac and the microcontroller. the usb processor consists of: the philips serial interface engine (psie) the memory management unit (mmu) the audio sample redistribution (asr) module. the philips serial interface engine and memory management unit (psie/mmu) the psie/mmu translates the electrical usb signals into bytes and signals. depending upon the usb device address and the usb endpoint address, the usb data is directed to the correct endpoint buffer on the psie/mmu interface. the data transfer could be of bulk, isochronous, control or interrupt type. the usb device address is con?gured during the enumeration process. the UDA1335H has four endpoints. these are: control endpoint 0 status interrupt endpoint isochronous data sink endpoint isochronous data source endpoint. the amount of bytes/packet on the control endpoint is limited by the psie/mmu hardware to 8 bytes/packet. the psie is the digital front-end of the usb processor. this module recovers the 12 mhz usb clock, detects the usb sync word and handles all low-level usb protocols and error checking. the mmu is the digital back-end of the usb processor. it handles the temporary data storage of all usb packets that are received or sent over the bus. three types of packets are defined on the usb. these are: token packets data packets handshake packets. the token packet contains information about the destination of the data packet. the audio data is transferred via an isochronous data sink endpoint or source endpoint and, consequently, no handshaking mechanism is used. the mmu also generates a 1 khz clock that is locked to the usb start of frame (sof) token. the audio sample redistribution (asr) the asr reads the audio samples from the mmu and distributes these samples equidistant over a 1 ms frame period. the distributed audio samples are translated by the digital i/o module to standard i 2 s-bus format or japanese digital i/o format. the asr generates the bit clock and the word select signal of the digital i/o. the digital i/o formats the received audio samples to one of the four speci?ed serial digital audio formats (i 2 s-bus, 16, 18 or 20 bits lsb-justi?ed). the microcontroller the microcontroller receives the control information selected from the usb by the usb processor. it handles the high-level usb protocols and the user interfaces. the major task of the software process, that is mapped upon the microcontroller, is to control the different modules of the UDA1335H in such a way that it behaves as a usb device. therefore the microcontroller: interprets the usb requests and maps them upon the UDA1335H application controls the internal operation of the UDA1335H, the digital i/o pins and the gp i/o pins communicates with the external world (external controller, eeprom) using the i 2 c-bus facility and the gp i/o pins. the microcontroller does not handle the audio stream. the UDA1335H will be delivered with usb compliant firmware. the firmware must be located in an external (e)prom.
1998 aug 28 10 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H the analog-to-digital interface (adif) the adif is used for sampling an analog input signal from a microphone or line input and sending the audio samples to the usb interface. the adif consists of a stereo programmable gain amplifier (pga), a stereo analog-to-digital converter (adc) and decimation filters (dfs). the sample frequency of the adc is determined by the adc clock (see section the timing of the analog-to-digital interface). the user can also select a digital serial input instead of an analog input. in this event the sample frequency is determined by the continuous ws clock with a range between 5 to 55 khz. digital serial input is possible with four formats (i 2 s-bus, 16, 18 or 20 bits lsb-justified). the programmable gain ampli?er circuit (pga) this circuit can be used for a microphone or line input. the input audio signals can be amplified by 7 different gains. the preferred gain is selected during start-up of the device (configuration map). the gain settings are given in table 1. table 1 the selectable gains of the pga the analog-to-digital converter (adc) the stereo adc of the UDA1335H consists of two 3rd-order sigma-delta modulators. they have a modified ritchie-coder architecture in a differential switched capacitor implementation. the oversampling ratio is 128. both adcs can be switched off in power saving mode (left and right separate). the adc clock is generated by the analog pll or the adc oscillator. setting gain unit 000 - 3db 001 0 db 010 3 db 011 9 db 100 15 db 101 21 db 11x 27 db the decimation filter (df) the decimator filter converts the audio data from 128f s down to 1f s with a word width of 8, 16 or 24 bits. this data will be transmitted over the usb as mono or stereo in 1, 2 or 3 bytes/sample. the decimator filters are clocked by the adc clock. the timing of the analog-to-digital interface the clock source of the adif is the analog pll or the adc oscillator. the preferred clock source can be selected during start-up of the device (configuration map). the adc clock used for the adc and decimation filters is obtained by dividing the clock signal coming from the analog pll or from the adc oscillator by a factor q. using the analog pll the user can select 3 clock frequencies via the microcontroller. by connecting the appropriate crystal the user can choose any clock signal between 8.192 and 14.08 mhz via the adc oscillator. table 2 the analog pll clock output frequencies the dividing factor q can be selected via the microcontroller. with this dividing factor q the user can select a range of adc clock signals allowing several different sample frequencies (see table 3). fcode apll clock frequency (mhz) 00 11.2896 01 8.1920 10 12.2880 11 11.2896
1998 aug 28 11 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H table 3 adc clock frequencies and sample frequencies based upon using the apll as a clock source (analog input topology 1), see note 1. note 1. by using the apll as a clock source 12 sample frequencies will be reported to the usb host. table 4 adc clock frequencies and sample frequencies based upon using the oscad as a clock source (analog input topology 4), see note 1 notes 1. by using the oscad as a clock source, the sample frequency and the q dividing factor must be filled in the configuration map. only this one sample frequency will be reported to the usb host. 2. the oscillator frequency (and therefore the crystal) of oscad must be between 8.192 and 14.08 mhz. 3. the q factor can be 1, 2, 4 or 8. 4. sample frequencies below 5 khz and above 55 khz are not supported. apll clock frequency (mhz) divide factor q adc clock frequency (mhz) sample frequency (khz) 8.1920 1 4.096 32 2 2.048 16 4 1.024 8 8 0.512 (not supported) 4 (not supported) 11.2896 1 5.6448 44.1 2 2.8224 22.05 4 1.4112 11.025 8 0.7056 5.5125 12.2880 1 6.144 48 2 3.072 24 4 1.536 12 8 0.768 6 oscad clock frequency (mhz) divide factor q adc clock frequency (mhz) sample frequency (khz) f osc (2) q (3) f osc /(2q) f osc /(256q) (4)
1998 aug 28 12 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H the asynchronous digital-to-analog converter (adac) the adac receives usb audio information from the usb processor or from the digital i/o-bus. the adac is able to reconstruct the sample clock from the rate at which the audio samples arrive and handles the audio sound processing. after the processing, the audio signal is upsampled, noise-shaped and converted to analog output voltages capable of driving a line output. the adac consists of: a sample frequency generator (sfg) fifo registers an audio feature processing dsp two digital upsampling filters and a variable hold register a digital noise shaper (ns) a filter stream dac (fsdac) with integrated filter and line output drivers. the sample frequency generator (sfg) the sfg controls the timing signals for the asynchronous digital-to-analog conversion. by means of a digital pll, the sfg automatically recovers the applied sampling frequency and generates the accurate timing signals for the audio feature processing dsp and the upsampling ?lters. first-in first-out (fifo) registers the fifo registers are used to store the audio samples temporarily coming from the usb processor or from the digital i/o input. the use of a fifo (in conjunction with the sfg) is necessary to remove all jitter present on the incoming audio signal. the audio feature processing dsp a dsp processes the sound features. the control and mapping of the sound features is explained in section controlling the usb aprp. depending on the sampling rate (f s ) the dsp knows four frequency domains in which the treble and bass are regulated. the domain is chosen automatically. table 5 frequency domains for audio processing by the dsp the upsampling ?lters and variable hold function after the audio feature processing dsp two upsampling filters and a variable hold function increase the oversampling rate to 128f s . the noise shaper a 3rd-order noise shaper converts the oversampled data to a noise-shaped bitstream for the fsdac. the in-band quantization noise is shifted to frequencies well above the audio band. the filter stream dac (fsdac) the fsdac is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. the filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. in this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. a post filter is not needed because of the inherent filter function of the dac. on-board amplifiers convert the fsdac output current to an output voltage signal capable of driving a line output. usb audio playback recording peripheral (aprp) descriptors in a typical usb environment the pc has to know which kind of devices are connected. for this purpose each device contains a number of usb descriptors. these descriptors describe, from different points of view (usb configuration, usb interface and usb endpoint), the capabilities of a device. each of them can be requested by the host. the collection of descriptors is denoted as a descriptor map. this descriptor map will be reported to the usb host during enumeration and on request. the usb descriptors and their most important fields, in relationship to the characteristics of the UDA1335H are explained briefly below. domain sample frequency (khz) 1 5 to 12 212to25 325to40 440to55
1998 aug 28 13 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H a udio function topologies four audio function input topologies and two audio function output topologies are supported by the UDA1335H. each configuration map can select only one input and one output topology. the descriptors and the supported requests depend on the selected topologies in the active configuration map. figures 3 and 4 illustrate the different audio input and output topologies. fig.3 one audio output function topology (with or without bass boost) is supported. handbook, full pagewidth mbk530 input terminal output terminal feature unit fu it ot handbook, full pagewidth su selector unit mgl437 analog input terminal output terminal output terminal output terminal output terminal analog input terminal digital input terminal input terminal 1 input terminal 2 it ot it ot it ot it it ot fig.4 four input function topologies are supported. c. digital topology 3. d. analog topology 4 (using oscad clock source). a. analog topology 1 (using apll clock source). b. analog topology 2.
1998 aug 28 14 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H g eneral descriptors the UDA1335H supports one configuration containing a control interface, two audio interfaces and a hid interface. the descriptor map that describes this configuration is partly fixed and partly programmable. the programmable part can be retrieved from one of four configuration maps located in the firmware or from an i 2 c-bus eeprom. at start-up time one of four internal configuration maps can be selected depending on the logical combination of gp3 and gp4. it is possible to overwrite this configuration map with a configuration map loaded from an i 2 c-bus eeprom. a udio device class specific descriptors the audio device class is partly specified with standard descriptors and partly with specific audio device class descriptors. the standard descriptors specify the number and the type of the interface or endpoint. the UDA1335H supports 7 different audio modes: 8-bit pcm mono or stereo audio data 16-bit pcm mono or stereo audio data 24-bit pcm mono or stereo audio data zero bandwidth mode. each mode is defined as an alternate setting of the audio interface, selectable with the standard audio streaming interface descriptor balternatesetting field. the seven alternate settings are described in more detail by the specific audio device class descriptors. the UDA1335H supports the input terminal, output terminal and the feature unit descriptors. the input and output terminals are not controllable via the usb. the feature unit provides the basic manipulation of the incoming logical channels. the supported sound features are: volume control mute control treble control bass control bass boost control. the maximum number of audio data samples within a usb packet arriving on the isochronous sink endpoint is restricted by the buffer capacity of this isochronous endpoint. the maximum buffer capacity is 336 bytes/ms. the input terminals can be defined by means of wterminaltype. t he standard audio streaming interface descriptor for the isochronous data sink endpoint in this section the descriptors are given for interface 1 which is used for receiving isochronous audio data from the host. although in this specific UDA1335H application no endpoint control properties can be used on the isochronous adaptive sink endpoint, the descriptors are still necessary to inform the host about the definition of this endpoint: isochronous, adaptive, sink, continuous sampling frequency (at input side of this endpoint) with a lower boundary of 5 khz and an upper boundary of 55 khz. the audio class specific descriptors can be requested with the get descriptor: configuration request, which returns all the descriptors, except the device descriptor. for each alternate setting with audio, a maximum bandwidth is claimed as indicated in the standard isochronous audio data endpoint descriptor wmaxpacketsize field. to allow a small overshoot in the number of audio samples per packet, the top sample frequency of 55 khz is taken in the calculation of the bandwidth for each alternate setting. for each alternate setting, with its own isochronous audio data endpoint descriptor, wmaxpacketsize field is then defined as described in table 6. table 6 audio bandwidth at each audio mode t he standard audio streaming interface descriptor for the isochronous data source endpoint interface 2 is used for sending isochronous audio data to the host. it has the same alternate settings as interface 1. alternate setting audio mode wmaxpacketsize (hex) 1 8-bit pcm, mono 3800 2 8-bit pcm, stereo 7000 3 16-bit pcm, mono 7000 4 16-bit pcm, stereo e000 5 24-bit pcm, mono a800 6 24-bit pcm, stereo 5001
1998 aug 28 15 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H h uman interface device specific descriptors the inputs defined on the UDA1335H are transmitted via the usb to the host according to the hid class. the host responds with the appropriate settings via the audio device class for the audio related parts or via the hid class for the hid related inputs and outputs of the UDA1335H. a hid descriptor is necessary to inform the host about the conception of the user interface. the host communicates via the hid device driver using either the control pipe or the interrupt pipe. the UDA1335H is using usb endpoint 0 (control pipe) to respond to the hid specific get/set report request to receive or transmit data from or to the UDA1335H. the UDA1335H uses the status interrupt endpoint as interrupt pipe for polling asynchronous data. the UDA1335H is a high-speed device. the maximum transaction size is 64 bytes per usb frame and the polling rate is defined at a maximum of every 1 ms. the host requests the configuration descriptor which includes the standard interface descriptor, the hid endpoint descriptor and the hid descriptor. the hid device driver of the host then requests the report descriptor. report descriptors are composed of pieces of information about the device. each piece of information is called an item. all items have a 1-byte prefix that contains the item tag, type and size. in the UDA1335H only the short item basic type is used. the hosts hid device driver will parse the report descriptor and the defined items. by examining all of these items, the hid class driver is able to determine the size and composition of data reports from the device. the main items of the UDA1335H are input reports. input reports are sent via the interrupt pipe (UDA1335H usb endpoint 3). input reports can be requested by the host via the control endpoint (usb endpoint 0). the UDA1335H supports a maximum of two push-buttons (six with i 2 c-bus expanders), which represent a certain feature of the UDA1335H. if pressed by the user the pushbutton will go to its on state, if not pressed the push-button will go back to its off state. for more information about the input functions of the UDA1335H see the application documentation of the device. controlling the usb aprp the sound features as defined in the usb device class definition for audio devices are mapped on the UDA1335H specific feature registers by the microcontroller. these specific sound features are: volume control (separate for left and right stereo channels, no master channel) mute control (only master channel) treble control (only master channel) bass control (only master channel) dynamic bass boost control (only master channel). these specific features can be activated via the host (audio device class requests) or via the gp i/o pins (hid plus audio device class requests). the user is able to download the necessary configuration data for different applications (definition of the function of the gp pins, with or without digital i/o functionality etc.) via the configuration map. the mapping and control of the standard usb audio features and UDA1335H specific features is described below. volume control volume control is possible via the host or via predefined gp i/o pins. the setting of 0 db is always referenced to the maximum available volume setting. table 7 gives the mapping of wvolume value (as defined in the usb device class definition for audio devices ) upon the actual volume setting of the usb aprp. when using the UDA1335H, the range is 0 db down to - 60 db (in steps of 1 db) and - db. independant control of left/right volume is possible. it should be noted that wvolume lsb b7 to b0 are not used. values above 0 db are returned as 0 db. the volume value at start-up of the device is defined in the selected configuration map. balance control is possible via the separate volume control option of both channels. therefore the characteristics of the balance control are equal to the volume control characteristics.
1998 aug 28 16 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H table 7 volume control characteristics wvolume (msb) volume usb side (db) volume usb aprp (db) b15 b14 b13 b12 b11 b10 b9 b8 00000000 0 0 11111111 - 1 - 1 11111110 - 2 - 2 11111101 - 3 - 3 11111100 - 4 - 4 11111011 - 5 - 5 11111010 - 6 - 6 11111001 - 7 - 7 11111000 - 8 - 8 11110111 - 9 - 9 11110110 - 10 - 10 ... ... ... ... ... ... ... ... ... ... 11000101 - 59 - 59 11000100 - 60 - 60 11000011 - 61 - 11000010 - 62 - ... ... ... ... ... ... ... ... ... ... 10000000 - -
1998 aug 28 17 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H mute control mute is one of the sound features as defined in the usb device class definition for audio devices . the mute control request data bmute controls the position of the mute switch. the position can be either on or off. when bmute is true the feature unit is muted. when bmute is false the feature unit is not muted. when the mute is active for the master channel, the value of the sample is decreased smoothly to zero following a raised cosine curve. there are 32 coefficients used to step down the value of the data, each one being used 32 times before stepping to the next. this amounts to a mute transition of 23 ms at f s = 44.1 khz. when the mute is released, the samples are returned to the full level again following a raised cosine curve with the same coefficients being used in reversed order. the mute, on the master channel is synchronized to the sample clock, so that operation always takes place on complete samples. a mute can be given via the host or by pressing a predefined gp pin. treble control the treble control is available for the master channel of the UDA1335H. the treble range is from 0 to 6 db in steps of 2 db. it should be noted that the negative treble values as defined in the usb device class definition for audio devices are not supported by the UDA1335H; values below 0 db are returned as 0 db. the corner frequency is 1500 hz. table 8 gives the mapping of the btreble value upon the actual treble setting of the usb aprp. table 8 treble control characteristics btreble treble usb host (db) treble usb aprp (db) b7 b6 b5 b4 b3 b2 b1 b0 00000000 0.00 0 00000001 0.25 00000010 0.50 00000011 0.75 00000100 1.00 00000101 1.25 2 00000110 1.50 00000111 1.75 00001000 2.00 00001001 2.25 00001010 2.50 00001011 2.75 00001100 3.00 00001101 3.25 4 ... 00010101 5.25 6 ... 00011101 7.25 6 ... 00100101 9.25 6 ... 01111111 31.75 6
1998 aug 28 18 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H bass control the bass control is available for the master channel of the UDA1335H. the bass range is from 0 to approximately 24 db in steps of 2 db. it should be noted that the negative bass values as defined in the usb device class definition for audio devices are not supported by the UDA1335H; values below 0 db are returned as 0 db. the corner frequency is 75 hz. table 9 gives the mapping of the bbass value upon the actual bass setting of the usb aprp. table 9 bass control characteristics bbass bass usb host (db) bass usb aprp (db) b7 b6 b5 b4 b3 b2 b1 b0 00000000 0.00 0 00000001 0.25 00000010 0.50 00000011 0.75 00000100 1.00 00000101 1.25 1.7 00000110 1.50 00000111 1.75 00001000 2.00 00001001 2.25 00001010 2.50 00001011 2.75 00001100 3.00 00001101 3.25 3.6 ... 00010101 5.25 5.4 ... 00011101 7.25 7.4 ... 00100101 9.25 9.4 ... 00101101 1 1.25 11.3 ... 00110101 13.25 13.3 ... 00111101 15.25 15.2 ... 01000101 17.25 17.3 ... 01001101 19.25 19.2 ... 00111011 21.25 21.2 ...
1998 aug 28 19 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H 01010101 23.25 23.2 ... 01100101 25.25 23.2 ... 01101101 27.25 23.2 ... 01110101 29.25 23.2 ... 01111101 31.25 23.2 ... 01111111 31.75 23.2 bbass bass usb host (db) bass usb aprp (db) b7 b6 b5 b4 b3 b2 b1 b0 dynamic bass boost control bass boost is one of the sound features as defined in the usb device class definition for audio devices . the bass boost control request data bbassboost controls the position of the bass boost switch. the position can be either on or off. when bbassboost is true the bass boost is activated. when bbassboost is false the bass boost is off. when clipping prevention is active, the bass is reduced to avoid clipping with high volume settings. bass boost is selectable via the configuration map. clipping prevention when clipping prevention is on and the sum of bass plus volume gives clipping, the bass is reduced. when clipping prevention is on and the sum of treble plus volume gives clipping, the treble is reduced. clipping prevention and clipping level are selectable via the configuration map. for more information about clipping prevention and the clipping level see the application documentation. de-emphasis de-emphasis is one of the properties which is not supported by the usb. de-emphasis for 44.1 khz can be predefined in the configuration map selected at start-up of the UDA1335H. start-up and con?guration of the UDA1335H s tart - up of the UDA1335H after power-on, an internal power-on reset signal becomes high after a certain rc time (r = 5000 w , c = c ref ). during 20 ms after power-on reset the UDA1335H has to initiate the internal settings. after the power-on reset the UDA1335H becomes master of the i 2 c-bus. the UDA1335H tries to read the eventually connected i 2 c-bus eeprom and if an dedicated eeprom is detected, the internal descriptors are overwritten and the selected port configuration is applied. if no eeprom is detected, the UDA1335H tries to read the logic levels of gp3 and gp4. a choice can be made from four configuration maps via these two gp pins. c onfiguration selection of the UDA1335H via a diode matrix the UDA1335H uses a configuration map to hold a number of specific configurable data on hardware, product, component and usb configuration level. at start-up, without eeprom, the UDA1335H will scan the logic levels of gp3 and gp4. with these two gp pins it is possible to select one of the four possible configuration maps which are held in the external (e)prom. this selection can be achieved via a diode matrix (see fig.5).
1998 aug 28 20 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H after selecting an internal configuration map the user cannot change the chosen settings for the gp pins, internal configuration, descriptors etc. the UDA1335H supports a maximum of two push-buttons (six with i 2 c-bus expanders), which represent a certain feature of the UDA1335H. the UDA1335H supports a maximum of three outputs for e.g. user leds. for more information about the four configuration maps located in the (e)prom and the input and output functions of the UDA1335H see the application documentation. c onfiguration options of the UDA1335H via an i 2 c- bus eeprom at start-up, the UDA1335H will address i 2 c-bus slave address 0 a0h and will check the first two byte locations of the i 2 c-bus device with 0 55h and 0 aah. if a match occurs, the UDA1335H assumes that this i 2 c-bus device is an eeprom which is dedicated to the UDA1335H. it will then read the configuration map stored in this eeprom instead of one of four configuration maps located in the firmware of the microcontroller. the layout of the configuration map is fixed, the values (except bytes 0 and 1) are user definable. if the user wants to change e.g. the manufacturer name this can be achieved via the eeprom code. the communication between the UDA1335H and the external i 2 c-bus device is based on the standard i 2 c-bus protocol given in the philips specification the i 2 c-bus and how to use it (including specifications) , which can be ordered using the code 9398 393 40011. the i 2 c-bus has two lines; a clock line scl and a serial data line sda (see fig.6). fig.5 diode matrix selection. handbook, full pagewidth mgl480 10 nf 10 nf 22 pf 22 pf 4 6 5 3 2 1 usb-b connector v bus 22 w 22 w d - gp5 gp4 gp3 d + 1.5 k w 22 k w 22 k w 22 k w 22 k w 22 k w 22 k w tr3 tr1 tr2 3.3 v 3.3 v 3.3 v 3.3 v 22 k w v bus 1 2 d2 1 2 d1 key 1 sw1 key 2 sw2
1998 aug 28 21 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth mbc611 p s sr p t su;sto t sp t hd;sta t su;sta t su;dat t f t high t r t hd;dat t low t hd;sta t buf sda scl fig.6 definition of timing of the i 2 c-bus.
1998 aug 28 22 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H table 10 control options for the UDA1335H via the eeprom con?guration map; note 1 byte (hex) affects comments bit value 0 recognition pattern do not change it 55h 1 recognition pattern do not change it aah 2 clocks control register selection adc clock source 7 0 = adc clock from apll 1 = adc clock from oscad divide factor 6 and 5 00 = adc clock divided-by-1 01 = adc clock divided-by-2 10 = adc clock divided-by-4 11 = adc clock divided-by-8 clock adac 4 0 clock 48 mhz internal 3 0 clock recovered psie/mmu 2 0 adc clock 1 0 power on oscad 0 0 3 reset generator and apll control register 00h 4 power control register analog modules 00h 5 asr control register robust word clock 7 1 serial i 2 s-bus output format 6 and 5 00 = i 2 s-bus 01 = 16-bit lsb 10 = 18-bit lsb 11 = 20-bit lsb phase inversion (right output) 4 0 = mono phase inversal off 1 = mono phase inversal on bits per sample modi 3 and 2 00 = reserved 01 = 8-bit audio 10 = 16-bit audio 11 = 24-bit audio mono or stereo operation 1 0 = mono 1 = stereo asr register start-up mode 0 1
1998 aug 28 23 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H 6 pga control register input terminal 1 (all analog input topologies) reserved 7 x pga internal setting (do not change it) 60 pga gain selection right channel 5 to 3 000 = - 3db 001 = 0 db 010 = 3 db 011=9db 100 = 15 db 101 = 21 db 110=27db 111 = 27 db pga gain selection left channel 2 to 0 000 = - 3db 001 = 0 db 010 = 3 db 011=9db 100 = 15 db 101 = 21 db 110=27db 111 = 27 db 7 pga control register input terminal 2 (only for analog input topology 2) reserved 7 x pga internal setting (do not change it) 60 pga gain selection right channel 5 to 3 000 = - 3db 001 = 0 db 010 = 3 db 011=9db 100 = 15 db 101 = 21 db 110=27db 111 = 27 db pga gain selection left channel 2 to 0 000 = - 3db 001 = 0 db 010 = 3 db 011=9db 100 = 15 db 101 = 21 db 110=27db 111 = 27 db byte (hex) affects comments bit value
1998 aug 28 24 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H 8 adif control register reserved 7 x number of bits per audio sample to be transmitted to the host 6 and 5 00 = reserved 01 = 8 bits audio samples 10 = 16 bits audio samples 11 = 24 bits audio samples mono/stereo selection 4 0 = mono 1 = stereo selection audio input channel 3 0 = digital serial audio input 1 = analog input selection high-pass ?lter of the decimation module 2 0 = high-pass ?lter off 1 = high-pass ?lter on i 2 s-bus input serial input format 1 and 0 00 = i 2 s-bus 01 = 16-bit lsb 10 = 18-bit lsb 11 = 20-bit lsb 9 adac feature setting register selection adac mode register 7 0 audio feature mode 6 and 5 11 de-emphasis 4 0 = de-emphasis off 1 = de-emphasis on channel manipulation 3 0 = l ? l, r ? r 1=l ? r, r ? l synchronous/asynchronous 2 0 mute control 1 1 reset adac 0 0 a adac lock mode register selection adac mode register 7 1 digital pll lock speed 6 and 5 00 digital pll lock mode 4 1 digital pll mode 3 and 2 00 serial i 2 s-bus input format 1 and 0 00 = i 2 s-bus 01 = 16-bit lsb 10 = 18-bit lsb 11 = 20-bit lsb byte (hex) affects comments bit value
1998 aug 28 25 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H b i/o selection register clipping 7 0 = clipping prevention off 1 = clipping prevention on expander 6 0 = no i 2 c-bus expander used 1= i 2 c-bus expander used selector output (gp2) 5 0 = selector state normal 1 = selector state inverted mute/standby expander 4 0 = mute 1 = standby mute/standby usb aprp 3 0 = mute 1 = standby output pin 3 2 polarity output pins output pin 2 1 0 = inverted logic output pin 1 0 1 = normal logic c output pin function 1 functions are available if declared in adc: 0 = mute led; 1 = dbb led d output pin function 2 e output pin function 3 fi 2 s-bus and topology selection register output i 2 s-bus 7 0 = no i 2 s-bus used 1=i 2 s-bus used 4-pin or 6-pin i 2 s-bus 6 only if i 2 s-bus is used: 0 = 4-pin i 2 s-bus 1 = 6-pin i 2 s-bus hid usage 5 0 = hid not included 1 = hid included reserved 4 x topology selection 3 low nibble: 1 = input topology 1 2 = input topology 2 3 = input topology 3 4 = input topology 4 all other values = input topology 1 2 1 0 10 rise time power ampli?er, steps of 20 ms 11 time between mute and play, steps of 1 s 12 time between mute and standby, steps of 5 s 13 selector preferred state (only applicable in input topology 2) 0 = terminal input 1 or terminal input 2 14 dbb value steps of 1 db with maximum 255 db 0 = no dbb active 1 to ff = dbb active 15 start-up volume value in db volume = - register value byte (hex) affects comments bit value
1998 aug 28 26 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H notes 1. an extensive description of the usb control options is available in the usb device class definition for audio devices . 2. the serial number is only supported in the external configuration map and not in the four internal configuration maps. the general purpose i/o pins (gp0 to gp5) and i 2 c-bus expander option the UDA1335H has 6 general purpose (gp) i/o pins; these are pins gp0 to gp5. these can be used either for digital i/o functions or for general purposes. there are basically three port configurations: no digital i/o communication 4-pin digital i/o communication 6-pin digital i/o communication. 16 maximum distortion in db 17 sample frequency lsb 18 mid 19 msb 1a/1b pointer to device descriptor 0030 1c/1d pointer to con?guration descriptor 0045 1e/1f pointer to hid descriptor 01f0 20/21 pointer to hid report descriptor 0210 22 number of string pointers (n + 1) maximum for n is 31 23/24 pointer to string 0 025e 25/26 pointer to string 1 0260 27/28 pointer to string 2 0290 29/2a pointer to string 3 02d0 :: 23 + 2n/ 24+2n pointer to string n 30 ? device descriptor 45 ? 1f0 ? con?guration descriptor including adc and hid descriptors 32 210 ? 212 ? wdescriptorlength hid report descriptor 25e ? string 0 language string 260 ? string 1 manufacturer string 290 ? string 2 product string 2d0 ? string 3 serial number (2) byte (hex) affects comments bit value
1998 aug 28 27 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H these port configurations can be chosen via the configuration map at start-up of the UDA1335H. the user can also make use of an i 2 c-bus expander. the usage of an i 2 c-bus expander (yes/no) can be indicated via the configuration map. some of the supported hid functions are located in the i 2 c-bus expander. if this expander is not used, the hid functions normally located in the expander must be declared as unassigned in the hid report descriptor. the bit which indicates if an external expander is used must then be put on zero. table 11 de?nition of the general purpose pins and i 2 c-bus expander pins; notes 1 to 6 notes 1. connect/disconnect: this pin can be used to avoid malfunction during initialisation phase of the UDA1335H. while initialization takes place, the usb can be kept disconnected while the software of the microcontroller reads in the configuration map. when the UDA1335H is ready, the usb becomes connected and enumeration can start. using the 6-pin i 2 s-bus, the connect/disconnect will be moved to the i 2 c-bus expander. 2. hid input 1 to 6 and interrupt input: a change on the expander can be signalled to the UDA1335H via the interrupt input. after detecting this signal the UDA1335H will decode the buttons. when no expander is used, the interrupt pin must be connected to the ground. the hid input pins and the interrupt input pin on the UDA1335H are scanned each 20 ms. if the interrupt in pin indicates a change on the expander, the expander input pins are scanned once. using the 6-pin i 2 s-bus, the interrupt pin is not available and the inputs on the expander are scanned every 20 ms. all input pins must have a pull-up resistor. 3. selector output: this pin can be used for switching the audio selector as illustrated in fig.4. if the configuration map does not request this output pin, the output is always low. 4. mute output: this output is activated if the isochronous signal is not available during a certain time. the output levels and the time are programmable in the configuration map. 5. standby output: this output is activated if the UDA1335H is muted during a certain time. the output levels and the time are programmable in the configuration map. 6. output pins 1 to 3: all the output pins are set via the i 2 c-bus. the function is according the configuration map. 7. for the i 2 c-bus expander, the pcf8574p remote 8-bit i/o expander for i 2 c-bus can be used. pins no i 2 s-bus usage 4-pin i 2 s-bus usage 6-pin i 2 s-bus usage general purpose i/o gp5 connect/disconnect connect/disconnect ws input gp4 hid input 2 bck output bck output gp3 hid input 1 ws output ws output gp2 selector output data output data output gp1 mute or standby output data input data input gp0 interrupt input interrupt input bck input i 2 c-bus expander; note 7 p0 hid input 3 hid input 3 connect/disconnect p1 hid input 4 hid input 4 hid input 4 p2 hid input 5 hid input 5 hid input 5 p3 hid input 6 hid input 6 hid input 6 p4 output pin 1 output pin 1 output pin 1 p5 output pin 2 output pin 2 output pin 2 p6 output pin 3 selector output selector output p7 mute or standby output mute or standby output mute or standby output
1998 aug 28 28 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H filter characteristics the overall filter characteristic of the UDA1335H in flat mode is given in the fig.7. the overall filter characteristic of the UDA1335H includes the filter characteristics of the dsp in flat mode plus the filter characteristic of the fsdac (f s = 44.1 khz) fig.7 overall filter characteristics of the UDA1335H. handbook, full pagewidth mgm110 volume (db) f (khz) 10 20 30 40 50 60 70 80 90 100 0 - 160 - 120 - 80 - 40 - 140 - 100 - 60 - 20 - 0
1998 aug 28 29 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H dsp extension port an external dsp can be used for adding extra sound processing features via the digital i/o-bus. the UDA1335H supports the standard i 2 s-bus data protocol and the lsb-justified serial data input format with word lengths of 16, 18 and 20 bits. using the 4-pin digital i/o-bus the UDA1335H device acts as a master, controlling the bck and ws signals. the period of the ws signal is determined by the number of samples in the 1 ms frame of the usb. this implies that the ws signal does not have a constant time period, but is jittery. using the 6-pin digital i/o-pins gp2, gp3 and gp4 are output pins (master) and gp0, gp1 and gp5 are input pins (slave). the characteristic timing of the i 2 s-bus input interface is illustrated in figs 8 and 9. fig.8 timing of digital i/o input signals. handbook, full pagewidth mgk003 ws right lsb msb left bck data t f t r t h;ws t s;ws t bck(h) t bck(l) t cy t s;dat t h;dat
1998 aug 28 30 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... b ook, full pagewidth lsb-justified format 16 bits lsb-justified format 18 bits lsb-justified format 20 bits left left left right right right 2 2 15 16 17 18 1 15 16 1 msb lsb b2 msb b2 b3 b4 b15 lsb b17 2 15 16 17 18 1 msb b2 b3 b4 lsb b17 2 15 16 17 18 19 20 1 msb b2 b3 b4 b5 b6 lsb b19 2 15 16 17 18 19 20 1 msb b2 b3 b4 b5 b6 lsb b19 2 15 16 1 msb lsb b2 b15 ws left right 3 2 1 3 2 1 msb b2 msb lsb lsb msb b2 > =8 > =8 bck data ws bck data ws bck data ws bck data input format i 2 s-bus mgk002 fig.9 input formats.
1998 aug 28 31 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. 2. equivalent to discharging a 200 pf capacitor through a 2.5 m h series conductor. thermal characteristics recommended operating conditions symbol parameter conditions min. typ. max. unit all digital i/os v i/o dc input/output voltage range - 0.5 - v dde v i o output current v dde = 5.0 v -- 4ma temperature values t j junction temperature 0 - 125 c t stg storage temperature - 55 - +150 c t amb operating ambient temperature 0 25 70 c electrostatic handling v es electrostatic handling note 1 - 3000 - +3000 v note 2 - 300 - +300 v symbol parameter conditions value unit r thj-a thermal resistance from junction to ambient in free air 48 k/w symbol parameter min. typ. max. unit v dde supply voltage periphery (i/o) 4.75 5.0 5.25 v v dd supply voltage (core) 3.0 3.3 3.6 v v i dc input voltage range for d+ and d - 0.0 - v dd v for vinl and vinr - 0.5v dd - v for digital i/os 0.0 - v dde v
1998 aug 28 32 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H dc characteristics v dde = 5.0 v; v dd = 3.3 v; t amb =25 c; f osc = 48 mhz; f s = 44.1 khz; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v dde digital supply voltage periphery 4.75 5.0 5.25 v v ddi digital supply voltage core 3.0 3.3 3.6 v v dda1 analog supply voltage 1 3.0 3.3 3.6 v v dda2 analog supply voltage 2 3.0 3.3 3.6 v v dda3 analog supply voltage 3 3.0 3.3 3.6 v v ddo operational ampli?er supply voltage 3.0 3.3 3.6 v v ddx crystal oscillator supply voltage 3.0 3.3 3.6 v i dde digital supply current periphery note 1 - 3.7 - ma i ddi digital supply current core - 39.0 - ma i dda1 analog supply current 1 - 3.6 - ma i dda2 analog supply current 2 - 8.0 - ma i dda3 analog supply current 3 - 0.9 9.0 (2) ma i ddo operational ampli?er supply current - 3.0 - ma i ddx crystal oscillator supply current - 1.2 13.0 (3) ma p tot total power dissipation - 200 - mw p ps total power dissipation in power saving mode note 4 - 1.2 - mw inputs/outputs d+ and d - v i static dc input voltage - 0.5 - v ddi v v o(h) static dc output voltage high r l =15k w connected to gnd 2.8 - 3.6 v v o(l) static dc output voltage low r l =15k w connected to v dd -- 0.3 v ? i lo ? high impedance data line output leakage current -- 10 m a v i(diff) differential input sensitivity 0.2 -- v v cm(diff) differential common mode range 0.8 - 2.5 v v se(r)(th) single-ended receiver threshold voltage 0.8 - 2.0 v c in transceiver input capacitance pin to gnd -- 20 pf
1998 aug 28 33 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H notes 1. this value depends strongly on the application. the specified value is the typical value obtained using the application diagram as illustrated in fig.10. 2. at start-up of the oscad oscillator. 3. at start-up of the osc48 oscillator. 4. exclusive the i dde current which depends on the components connected to the i/o pins. digital input pins v il low-level input voltage -- 0.3v dde v v ih high-level input voltage 0.7v dde - v dde v ? i li ? input leakage current -- 1 m a c i input capacitance -- 5pf pga and adc v ref(ad) reference voltage pga and adc - 0.5v dda2 - v v ref(adc)(pos) positive reference voltage of the adc - v dda2 - v v ref(adc)(neg) negative reference voltage of the adc - 0.0 - v v i(pga) dc input voltage vinl and vinr of the pga - 0.5v dda2 - v r i(pga) dc input resistance at vinl and vinr of the pga - 12.5 - k w filter stream dac v ref(da) reference voltage dac - 0.5v dda1 - v v o(cm) common mode output voltage - 0.5v dda1 - v r o(vout) output resistance at voutl and voutr - 11 -w r o(l) output load resistance 2.0 -- k w c o(l) output load capacitance -- 50 pf symbol parameter conditions min. typ. max. unit
1998 aug 28 34 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H ac characteristics v dde = 5.0 v; v ddi = 3.3 v; t amb =25 c; f osc = 48 mhz; f s = 44.1 khz; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit driver characteristics d+ and d- (full-speed mode) f o(s) audio sample output frequency 5 - 55 khz t r rise time c l =50pf 4 - 20 ns t f fall time c l =50pf 4 - 20 ns t rf(m) rise/fall time matching (t r /t f )90 - 110 % v cr output signal crossover voltage 1.3 - 2.0 v r o(drive) driver output resistance steady-state drive 28 - 43 w data source timings d+ and d- (full-speed mode) f i(s) audio sample input frequency 5 - 55 khz f fs(d) full speed data rate 11.97 12.00 12.03 mbits/s t fr(d) frame interval 0.9995 1.0000 1.0005 ms t j1(diff) source differential jitter to next transition - 3.5 +0.0 +3.5 ns t j2(diff) source differential jitter for paired transitions - 4.0 +0.0 +4.0 ns t w(eop) source end of packet width 160 - 175 ns t eop(diff) differential to end of packet transition skew - 2.0 - +5.0 ns t jr1 receiver data jitter tolerance to next transition - 18.5 0.0 +18.5 ns t jr2 receiver data jitter tolerance for paired transitions - 9.0 0.0 +9.0 ns t eopr1 end of packet width at receiver must reject as end of packet 40 -- ns t eopr2 end of packet width at receiver must accept as end of packet 82 -- ns serial input/output data timing f s system clock frequency - 12 - mhz f i(ws) word selection input frequency 5 - 55 khz t r rise time -- 20 ns t f fall time -- 20 ns t bck(h) bit clock high time 55 -- ns t bck(l) bit clock low time 55 -- ns t s;dat data set-up time 10 -- ns t h;dat data hold time 20 -- ns t s;ws word selection set-up time 20 -- ns t h;ws word selection hold time 10 -- ns
1998 aug 28 35 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H sda and scl lines (standard mode i 2 c-bus) f scl scl clock frequency 0 - 100 khz t buf bus free time between a stop and start condition 4.7 -- m s t hd;sta hold time (repeated) start condition 4.0 -- m s t low low period of the scl clock 4.7 -- m s t high high period of the scl clock 4.0 -- m s t su;sta set-up time for a repeated start condition 4.7 -- m s t su;sto set-up time for stop condition 4.0 -- m s t hd;dat data hold time 5.0 - 0.9 m s t su;dat data set-up time 250 -- ns t r rise time of both sda and scl signals -- 1000 ns t f fall time of both sda and scl signals -- 300 ns c l(bus) capacitive load for each bus line -- 400 pf oscillator 1 (system clock) f osc oscillator frequency - 48 - mhz d duty factor - 50 - % g m transconductance 12.8 22.1 30.2 ms r o output resistance 0.6 1.1 2.3 k w c i(xtal1a) parasitic input capacitance xtal1a 4.5 4.8 5.2 pf c i(xtal2a) parasitic input capacitance xtal2a 4.1 4.6 5.0 pf i start start-up current 3.7 7.6 13.0 ma oscillator 2 (for adc clock) f osc oscillator frequency 8.192 - 14.08 mhz d duty cycle - 50 - % g m transconductance 8.1 13.6 18.1 ma/v r o output resistance 1.3 2.0 4.0 k w c i(xtal1b) parasitic input capacitance xtal1b 5.0 5.4 5.7 pf c i(xtal2b) parasitic input capacitance xtal2b 4.1 4.6 5.0 pf i start start-up current 2.4 5.0 8.4 ma symbol parameter conditions min. typ. max. unit
1998 aug 28 36 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H analog pll (for adc clock) f clk(pll) pll clock frequency 8.1920 11.2896 12.2880 mhz d duty factor - 50 - % t strt(po) start-up time after power-on -- 10 ms power-on reset t su(po) power-on set-up-time note 1 5c ref (2) -- ms pga and adc v i(fs)(rms) full-scale input voltage (rms value) pga gain = - 3db - 1414 (5) - mv pga gai n=0db - 1000 - mv pga gai n=3db - 708 - mv pga gai n=9db - 355 - mv pga gain = 15 db - 178 - mv pga gain = 21 db - 89 - mv pga gain = 27 db - 44 - mv c i(pga) input capacitance of the pga -- 20 pf (thd + n)/s total harmonic distortion plus noise-to-signal ratio f s = 44.1 khz at input signal of 1 khz; pga gain = 0 db; note 3 v i (0 db) (1.0 v rms) -- 85 - 80 db - 0.0056 0.01 % v i (- 60 db) -- 30 - 20 db - 3.2 10.0 % s/n signal to noise ratio v i = 0.0 v 90 95 - dba a ct crosstalk between channels pga gai n=0db - 100 - db f s sample frequency (128f s ) 0.640 - 7.04 mhz ol (fs) full-scale digital output level pga gai n=0db; v i = 1 v (rms) -- 2.0 - db symbol parameter conditions min. typ. max. unit
1998 aug 28 37 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H notes 1. strongly depends on the external decoupling capacitor connected to v ref(da) . 2. c ref in m f. 3. measured with the apll as adc clock source. 4. measured with i 2 s-bus input as digital source. 5. although a level of 1.414 v (rms) would be required to optimal drive the adc in this gain setting, this level can not be used. due to the 3.3 v supply voltage input, signals of 1.17 v (rms) and higher will result in clipping. application information the UDA1335H can only be used in combination with an external (e)prom. this (e)prom can be connected to the port pins (p0 and p2) of the UDA1335H and must contain the firmware for the microcontroller. the UDA1335H will be delivered with standard usb compliant firmware. the i 2 c-bus eeprom is optional and can be used to configure client specific configurations and descriptors. more information about the firmware, descriptors and configurations can be obtained from several application notes. filter stream dac res resolution 16 -- bits v o(fs)(rms) full-scale output voltage (rms value) v dd = 3.3 v - 0.66 - v svrr supply voltage ripple rejection at v dda and v ddo f ripple = 1 khz; v ripple(p-p) = 0.1 v - 60 - db ?d v o ? channel unbalance maximum volume - 0.03 - db a ct crosstalk between channels r l =5k w- 95 - db (thd + n)/s total harmonic distortion plus noise-to-signal ratio f s = 44.1 khz; r l =5k w ; note 4 at input signal of 1 khz (0 db) -- 90 - 80 db - 0.0032 0.01 % at input signal of 1 khz ( - 60 db) -- 30 - 20 db - 3.2 10 % s/n signal-to-noise ratio at bipolar zero a-weighting at code 0000h 90 95 - db symbol parameter conditions min. typ. max. unit
1998 aug 28 38 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H fig.10 application diagram (continued in fig.11). handbook, full pagewidth 17 gp0/bcki 15 gp5/wsi 13 gp1/di 6 d - 8 d + 12 v dde 11 v sse 9 v ddi 10 38 39 v ssi UDA1335H + v d 100 nf (63 v) 100 nf (63 v) c27 c26 r25 1 w l3 blm32a07 + v c + v d + v c + v a 100 nf (63 v) 100 nf (63 v) c24 c25 r17 1 w l2 blm32a07 blm32a07 4.7 pf (50 v) c37 12 pf (63 v) c38 + v a 100 nf (63 v) 47 m f (16 v) c34 c38 r35 1 w + v c 25 xtal1b 26 xtal2b r48 1.5 k w 47 vinr r7 22 w r16 22 w 61 bck 59 ws 57 da x4 digital input playback digital input recording bcki wsi di bck ws da c18 22 pf (63 v) c17 22 pf (63 v) c16 10 nf (50 v) 1 l1 8 2 7 3 6 45 v dda1 v ssa1 42 44 + v a 100 nf (63 v) 47 m f (16 v) c32 c21 r27 1 w v dda2 v ssa2 1 53 xtal2a 54 xtal1a 10 nf (63 v) c44 l5 1.5 m h v usb c47 100 m f (16 v) c46 100 m f (16 v) c45 100 m f (16 v) c6 18 pf (50 v) c5 18 pf (50 v) 10 nf (50 v) c15 x1 48 mhz adc xtal l8 blm32a07 l7 blm32a07 l6 v d(ext) v a(ext) gnd mbk839 4 3 2 1 c8 47 m f (16 v) 43 vinl c22 47 m f (16 v) analog input recording
1998 aug 28 39 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H fig.11 application diagram (continued from fig.10). handbook, full pagewidth r28 4.7 k w mbk840 56 p0.0 58 p0.1 60 p0.2 62 p0.3 64 p0.4 3 p0.5 5 p0.6 7 p0.7 50 ale 14 p2.0 16 p2.1 18 p2.2 20 p2.3 22 p2.4 23 p2.5 21 sda 19 scl 31 psen 18 17 14 1 a0 2 a1 3 a2 4 v ss 8 v dd 7 ptc 6 scl 5 sda 13 8 7 4 3 11 le 2 gp4/bcko 1 gp3/wso 63 28 gp2/do 36 rtcb 35 tc 4 shtcb v ddx 24 v ssx 32 v ddo 33 v sso 1 19 16 15 12 9 6 5 2 oe 74hct373d d1 d2 d4 UDA1335H pcf85116-3 10 a0 9 a1 8 a2 7 a3 6 a4 4 a6 5 a5 3 a7 24 a9 25 a8 21 a10 2 11 12 13 15 16 17 18 19 28 14 a12 23 a11 o0 o1 o2 o3 o4 o5 o6 o7 eepm27128 26 a13 22 oe 48 ea 20 ce 27 pgm 1 v pp + v d + v c 100 nf (63 v) 100 nf (63 v) c18 c28 r26 1 w l13 blm32a07 + v a 100 nf (63 v) 47 m f (16 v) c39 c33 r43 1 w 40 v ref(da) 34 voutl r38 10 k w r39 10 k w bcko wso do 1 2 (i 2 c-bus) c35 r20 1 w 47 m f (16 v) c48 47 m f (16 v) 37 voutr c41 47 m f (16 v) c29 100 nf (63 v) c36 100 nf (63 v) 41 v ref(ad) c31 47 m f (16 v) c28 100 nf (63 v) + v d + v d + v d v cc gnd c25 100 nf (50 v) 20 10 + v d v cc gnd c24 100 nf (50 v) 52 55 + v a 100 nf (63 v) 47 m f (16 v) c7 c19 r10 1 w v dda3 v ssa3 51 49 + v a 100 nf (63 v) c11 r8 1 w vrp vrn digital output playback analog output playback d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7
1998 aug 28 40 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 14.1 13.9 1 18.2 17.6 1.2 0.8 7 0 o o 0.2 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot319-2 95-02-04 97-08-01 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.2 0.8 d e q e a 1 a l p detail x l (a ) 3 b 19 y c e h a 2 d z d a z e e v m a 1 64 52 51 33 32 20 x pin 1 index b p d h b p v m b w m w m 0 5 10 mm scale qfp64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot319-2 a max. 3.20
1998 aug 28 41 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. caution wave soldering is not applicable for all qfp packages with a pitch (e) equal or less than 0.5 mm. if wave soldering cannot be avoided, for qfp packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 aug 28 42 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1998 aug 28 43 philips semiconductors preliminary speci?cation universal serial bus (usb) audio playback recording peripheral (aprp) UDA1335H notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1998 sca60 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 545102/750/01/pp44 date of release: 1998 aug 28 document order number: 9397 750 03922

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